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Exam 1 Review B

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Problem R1b.1.

Suppose we can divide the execution of an instruction into eight possible pipeline stages:

S0:0.20 ns
S1:0.05 ns
S2:0.10 ns
S3:0.15 ns
S4:0.05 ns
S5:0.20 ns
S6:0.10 ns
S7:0.15 ns

However, inserting pipeline registers between stages requires adding 0.05 ns to the time for the stage.

a. If we use this proposed 8-stage pipeline, how long must each clock cycle be?

b. Now suppose that you want to combine stages while maintaining the same clock rate. Which pipeline stages would you combine? How many stages result?

c. Now suppose that you want to combine stages with each clock cycle taking 0.05 ns longer. Which pipeline stages would you combine? How many stages result?

d. Usually more stages enables a faster clock, which means that instructions are completed more quickly. Explain why sometimes fewer stages will enable instructions to complete more quickly.